/*
Copyright (c) 2019 Alibaba Group Holding Limited

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/
module is_pmu_top(
input wire        cpu_ispmu_dfs_ack,
input wire        cpu_ispmu_sleep_b,
output wire       dft_clk,
input wire        ehs_ispmu_clk,
output wire       pad_core_clk,
output wire       pad_core_ctim_refclk,
output wire       pad_core_rst_b,
input wire        pad_mcurst_b,
output wire       ispmu_cpu_dfs_req,
output wire       ispmu_dummy4_hclk,
output wire       ispmu_dummy4_hrst_b,
output wire       ispmu_mdummy3_hclk,
output wire       ispmu_mdummy3_hrst_b,
output wire       ispmu_dmemdummy0_hclk,
output wire       ispmu_dmemdummy0_hrst_b,
output wire       ispmu_dummy0_hclk,
output wire       ispmu_dummy0_hrst_b,
output wire       ispmu_dummy1_hclk,
output wire       ispmu_dummy1_hrst_b,
output wire       ispmu_dummy2_hclk,
output wire       ispmu_dummy2_hrst_b,
output wire       ispmu_dummy3_hclk,
output wire       ispmu_dummy3_hrst_b,
output wire       ispmu_hmain0_hclk,
output wire       ispmu_hmain0_hrst_b,
output wire       ispmu_imemdummy0_hclk,
output wire       ispmu_imemdummy0_hrst_b,
output wire       ispmu_mdummy0_hclk,
output wire       ispmu_mdummy0_hrst_b,
output wire       ispmu_mdummy1_hclk,
output wire       ispmu_mdummy1_hrst_b,
output wire       ispmu_mdummy2_hclk,
output wire       ispmu_mdummy2_hrst_b,
output wire       ispmu_smc_hclk,
output wire       ispmu_smc_hrst_b,
output wire       ispmu_wic_intr,
input wire        wdt_ispmu_rst_b
);
wire ispmu_apb0_pclk_en;
wire ispmu_apb1_pclk_en;
wire soc_hclk;
wire sys_rst_b;
wire soc_hrst_b;

assign ispmu_cpu_dfs_req = 1'b0;
assign ispmu_wic_intr = 1'b0;
assign ispmu_apb0_pclk_en = 1'b1;
assign ispmu_apb1_pclk_en = 1'b1;
assign  soc_hclk = ehs_ispmu_clk;
assign  dft_clk = ehs_ispmu_clk;
assign sys_rst_b = pad_mcurst_b & wdt_ispmu_rst_b;
assign  soc_hrst_b  = sys_rst_b;
assign  pad_core_clk = soc_hclk;
assign  pad_core_ctim_refclk = soc_hclk;
assign  ispmu_mdummy3_hclk = soc_hclk;
assign  ispmu_dummy4_hclk = soc_hclk;
assign  ispmu_imemdummy0_hclk = soc_hclk;
assign  ispmu_dmemdummy0_hclk = soc_hclk;
assign  ispmu_dummy0_hclk = soc_hclk;
assign  ispmu_dummy1_hclk = soc_hclk;
assign  ispmu_dummy2_hclk = soc_hclk;
assign  ispmu_dummy3_hclk = soc_hclk;
assign  ispmu_hmain0_hclk = soc_hclk;
assign  ispmu_mdummy0_hclk = soc_hclk;
assign  ispmu_mdummy1_hclk = soc_hclk;
assign  ispmu_mdummy2_hclk = soc_hclk;
assign  ispmu_smc_hclk = soc_hclk;
assign  pad_core_rst_b = soc_hrst_b;
assign  ispmu_mdummy3_hrst_b = soc_hrst_b;
assign  ispmu_dummy4_hrst_b = soc_hrst_b;
assign  ispmu_imemdummy0_hrst_b = soc_hrst_b;
assign  ispmu_dmemdummy0_hrst_b = soc_hrst_b;
assign  ispmu_dummy0_hrst_b = soc_hrst_b;
assign  ispmu_dummy1_hrst_b = soc_hrst_b;
assign  ispmu_dummy2_hrst_b = soc_hrst_b;
assign  ispmu_dummy3_hrst_b = soc_hrst_b;
assign  ispmu_hmain0_hrst_b = soc_hrst_b;
assign  ispmu_mdummy0_hrst_b = soc_hrst_b;
assign  ispmu_mdummy1_hrst_b = soc_hrst_b;
assign  ispmu_mdummy2_hrst_b = soc_hrst_b;
assign  ispmu_smc_hrst_b = soc_hrst_b;
endmodule
